Processing systems may utilize watchdog timers to detect errors in software running on the processing system. A watchdog timer is typically implemented as a counter loaded with a specified time out value, which continually counts down from the time out value. Under normal system operation, a reset signal received from the processing system causes the watchdog timer to reload the initial time out value at regular intervals. The reset signal may occur, for example, each time a certain number of lines of software code are executed by the processing system. If the watchdog timer does not receive the reset signal within a given amount of time, as in the case of a software error, the counter runs to zero and triggers a reset of the processing system.
Generally, the time out value of the counter is set during the initial design of the microcontroller or other processing system implementing the watchdog timer. For security purposes, the time out value of the counter is locked during operation of the processing device. Disallowing reconfiguration of the watchdog timer prevents errors in the software from corrupting the watchdog timer and from possibly preventing a system reset.
In certain instances, the processing system may have more than one mode of operation, such as a high speed mode or a low power mode. In a low power mode, for example, the processing system may execute the software code at a lower frequency that in a normal mode. Since the reset signal is provided to the watchdog timer at an interval based on the number of lines of code that have been executed, a lower frequency causes the reset signal to be sent less often. Accordingly, the counter in the watchdog timer is loaded with a large time out value or the counter may reach zero before the next reset signal, mistakenly indicating a software error.